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INTEGRATED CIRCUITS
DATA SHEET
UDA1309H Low-power stereo bitstream ADC/DAC
Product specification Supersedes data of 1996 Jul 18 File under Integrated Circuits, IC01 1998 Jan 06
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
FEATURES * Low power * Integrated high-pass filter to cancel DC offset (ADC) * Analog loop-through function * Multiple digital input/output formats possible * 256fs system clock frequency * Several power-down modes * Digital de-emphasis (DAC) * Overload detector to enable automatic recording level adjustment (ADC) * High dynamic range * DAC requires only one capacitor for post-filtering * Small 44-pin quad flat pack with 0.8 mm pitch * 256fs system clock frequency in Analog-to-Digital (AD) and Digital-to-Analog (DA) mode * Choice of three system clock frequencies (192fs, 256fs or 384fs) in DA mode. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION GENERAL DESCRIPTION APPLICATION * Portable digital audio equipment.
UDA1309H
The UDA1309H is a single chip stereo analog-to-digital and digital-to-analog converter employing bitstream conversion techniques. The device is eminently suitable for use in low-power portable digital audio equipment which incorporates recording and playback functions.
VERSION
UDA1309H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
1998 Jan 06
2
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
QUICK REFERENCE DATA VDDD = VDDA = VDDO = VDDD(F) = 5 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 C; full scale sine wave input; mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless otherwise specified. SYMBOL Supply VDDA(AD) VDDA(DA) VDDO VDDD VDDD(F) IDDA(AD) IDDA(DA) IDDO IDDD IDDD(F) Tamb VI(rms) ADC analog supply voltage (pin 8) DAC analog supply voltage (pin 25) operational amplifiers supply voltage (pin 19) ADC and DAC digital supply voltage (pin 28) digital filters supply voltage (pin 34) ADC analog supply current (pin 8) DAC analog supply current (pin 25) operational amplifiers supply current (pin 19) ADC and DAC digital supply current (pin 28) digital filters supply current (pin 34) operating ambient temperature 4.5 4.5 4.5 4.5 4.5 - - - - - -20 5.0 5.0 5.0 5.0 5.0 9 4.5 14 0.2 24 - 5.5 5.5 5.5 5.5 5.5 13.5 6.8 21 0.5 36 +75 V V V V V mA mA mA mA mA C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Analog-to-digital converter input voltage (RMS value) note 1 at 0 dB at -60 dB; A-weighted VI = 0 V; A-weighted 0.9 - - tbf - 1.0 -85 -35 95 90 1.1 tbf -30 - - V dB dB dB dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N cs VO(rms) idle channel signal-to-noise ratio channel separation
Digital-to-analog converter output voltage (RMS value) note 2 at 0 dB at -60 dB; A-weighted at -60 dB; A-weighted; note 3 S/N cs Notes 1. VI for full scale digital output is a function of VDDA(AD) [1.0 V (RMS) at VDDA(AD) = 5.0 V is equivalent to -1.0 dB in the digital domain]. 2. At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA). 3. 18-bit input data. idle channel signal-to-noise ratio channel separation code 0000H; A-weighted 0.9 - - - - 90 1.0 -90 -38 -44 104 100 1.1 -82 -34 - - - V dB dB dB dB dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio
1998 Jan 06
3
ook, full pagewidth
analog input VIL
1998 Jan 06
analog output VOL 1 nF VDDA(DA) CLKEDGE VSSD(F) VSSA(DA) DADEM TEST0 MODE2 VDDO MODE1 TEST1 VDDD(F) SYSCLK MODE0 VSSO 38 3 1.6 k 30 26 37 44 43 42 33 20 34 25 19 DACL 22 VOL 21 MODE SELECT DAC DIGITAL INTERFACE DIGITAL FILTER DIGITAL INTERFACE Vm 18 DAref 0.22 F 10 F
47 F
VDDA(AD)
4.7 k
BLOCK DIAGRAM
330 pF
0.22 F
Philips Semiconductors
4.7 k
0.22 F
Vref
10
BAIL 13
BAOL Vref(pos) Vref(neg) 12 11 40 9
VSSA(AD) 7
VDDA(AD) 8
ADC
Iref 17
CURRENT IDAC REFERENCE
47 k
DIGITAL FILTER
Low-power stereo bitstream ADC/DAC
4
DAC
ADC
Vm 5 4 1 2 41 6
UDA1309H
1.6 k 27 28 VDDD VSSD 23 DACR 1 nF 36 32 31 35 29 39 VSS(I/O) 24 VOR
16
14
15
ADref
BAIR
BAOR
0.22 F
4.7 k
330 pF
4.7 k
DAPON ADENB DASDA ADWS DABCK ADBCK DAWS ADSDA OVLOAD ADPON ANLPTR
analog output VOR
MBH527
47 F
analog input VIR
Supply decoupling on pins 19, 25, 28 and 34; 0.22 F (ceramic), 47 F (electrolytic). Capacitance at pin 11 should be close to pins 11 and 9.
Product specification
UDA1309H
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
PINNING SYMBOL ADBCK ADWS MODE0 ADENB OVLOAD ADPON VSSA(AD) VDDA(AD) Vref(neg) Vref Vref(pos) BAOL BAIL BAIR BAOR ADref Iref DAref VDDO VSSO VOL DACL DACR VOR VDDA(DA) VSSA(DA) VSSD VDDD DAPON DADEM DABCK DAWS VSSD(F) VDDD(F) DASDA ANLPTR TEST0 TEST1 VSS(I/O) SYSCLK 1998 Jan 06 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ADC input bit clock; 32fs or 64fs ADC word select input at fs ADC/DAC mode select input ADC serial data enable input (active HIGH) ADC output overload flag (active LOW) ADC power-on-mode input (active HIGH) ADC analog ground supply voltage ADC analog supply voltage ADC negative reference voltage input (ground) ADC decoupling capacitor ADC positive reference voltage decoupling capacitor ADC input amplifier output left ADC input amplifier virtual ground left ADC input amplifier virtual ground right ADC input amplifier output right ADC decoupling capacitor ADC/DAC reference current resistor input DAC decoupling capacitor ADC/DAC operational amplifier supply voltage ADC/DAC operational amplifier ground supply voltage DAC output voltage left DAC output current left DAC output current right DAC output voltage right DAC analog supply voltage DAC analog ground supply voltage ADC/DAC digital ground supply voltage ADC/DAC digital supply voltage DAC power-on-mode input (active HIGH) DAC digital de-emphasis input (active HIGH) DAC input bit clock; 32fs, 48fs or 64fs DAC word select input at fs ADC/DAC digital filters ground supply voltage ADC/DAC digital filters supply voltage DAC serial data input ADC/DAC analog loop-through input (active HIGH) ADC/DAC enable test mode 0 input (LOW is normal mode) ADC/DAC enable test mode 1 input (LOW is normal mode) ADC/DAC digital input/output ground supply voltage DESCRIPTION
UDA1309H
ADC/DAC system clock input (fsys = 256fs; DAC also 192fs and 384fs) 5
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
SYMBOL ADSDA MODE1 MODE2 CLKEDGE
PIN 41 42 43 44 ADC serial data output ADC/DAC mode 1 select input ADC/DAC mode 2 select input
DESCRIPTION
ADC/DAC input bit clock rising/falling edge
34 VDDD(F)
36 ANLPTR
39 VSS(I/O)
40 SYSCLK
handbook, full pagewidth
44 CLKEDGE
42 MODE1
43 MODE2
41 ADSDA
35 DASDA
37 TEST0
38 TEST1
ADBCK ADWS MODE0 ADENB OVLOAD ADPON VSSA(AD) VDDA(AD) Vref(neg)
1 2 3 4 5 6 7 8 9
33 VSSD(F) 32 DAWS 31 DABCK 30 DADEM 29 DAPON
UDA1309H
28 VDDD 27 VSSD 26 VSSA(DA) 25 VDDA(DA) 24 VOR 23 DACR
Vref 10 Vref(pos) 11
VOL 21
BAOL 12
BAOR 15
VDDO 19
VSSO 20
DACL 22
13
BAIR 14
ADref 16
Iref 17
DAref 18
BAIL
MBH526
Fig.2 Pin configuration.
1998 Jan 06
6
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
FUNCTIONAL DESCRIPTION Figure 1 illustrates the various components of the UDA1309H. The analog-to-digital converter is a bitstream type converter, both channels are sampled simultaneously. The digital-to-analog converter is a BCC (Bitstream Continuous Calibration) type converter. The digital filter for the ADC is a bit serial IIR filter that produces a fairly linear phase response up to 15 kHz. A high-pass filter is incorporated in the down-sampling path to remove DC offsets. An overload detection circuit is incorporated to facilitate automatic recording level adjustment. The digital up-sample filter for the DAC is partly IIR, with virtual linear phase response up to 15 kHz, and partly FIR. A switchable digital de-emphasis circuit is also incorporated. Due to the BCC principle used, the DAC needs only single pole post-filtering (one external capacitor) to meet the out-of-band suppression requirement. The ADC and DAC channels have separate power-down modes, to reduce power if one of them is not in use. An analog loop-through function enables analog-input analog-output mode without using the ADC and DAC converters or filters, thereby switching them off to reduce power consumption. Table 1 Interface mode selection DEVICE PIN MODE 2 0 0 0 0 1 1 1 1 Note 1. Only digital-to-analog. Table 2 Clock edge mode VALID EDGE OF BCK CLKEDGE ADC 0 1 1998 Jan 06 falling rising 7 MODE 1 0 0 1 1 0 0 1 1 MODE 0 0 1 0 1 0 1 0 1 TYPE LSB justified LSB justified LSB justified LSB justified I2S-bus I2S-bus I2S-bus I2S-bus BITS 16 16 16 18 16 16 16 18 ADC/DAC FORMATS BCK 32fs 64fs 48fs 64fs 32fs 64fs 48fs 64fs
UDA1309H
The digital interfaces accommodates, 16 and 18-bit, I2S-bus and LSB justified formats. The ADC digital output can be made 3-state by means of the ADENB signal, this enables the use of a digital bus. The UDA1309H interface accommodates slave mode only, therefore, the system ICs must provide the system clock, bit clock and word clock signals. For the DAC, the UDA1309H accepts the data together with these clocks, for the ADC it delivers the data in response to these clocks. Within one stereo frame, the first sample always represents the left channel. When sending data the unused bit positions are set to zero, when receiving data these bit positions are don't cares. To accommodate the various interface formats and system clock frequencies four control pins are provided, MODE0 to MODE2 for mode selection and CLKEDGE which selects the active edge of the BCK signal. Table 1 gives the interface mode selection, Fig.3 illustrates the ADC/DAC data formats and Fig.5 the operating modes. The section of the UDA1309H is designed to accommodate two main modes: 1. The 256fs mode in which analog-to-digital and digital-to-analog can be used. 2. The 192fs or 384fs mode (digital-to-analog only).
SYS; fsys 256fs 256fs 192fs 256fs 256fs 256fs 384fs(1) 256fs
(1)
FIGURE 3(a) 3(b) 4(a) 3(c) 3(d) 3(e) 4(b) 3(f)
DAC rising falling
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
handbook, full pagewidth
LSB JUSTIFIED 32fs 16-BIT
BCK WS SDA LSB MSB LSB MSB (a) LSB JUSTIFIED 64fs 16-BIT BCK WS SDA LSB MSB LSB (b) LSB JUSTIFIED 64fs 18-BIT BCK WS SDA LSB MSB LSB (c) I2S 32fs 16-BIT BCK WS SDA LSB MSB LSB MSB (d) I2S 64fs 16-BIT BCK WS SDA MSB LSB MSB (e) I2S 64fs 18-BIT BCK WS SDA MSB LSB (f) MSB LSB MSB
MGE767
LEFT
RIGHT
LSB MSB
LEFT
RIGHT
MSB
LSB
LEFT
RIGHT
MSB
LSB
LEFT
RIGHT
LSB
LEFT
RIGHT
LSB
MSB
LEFT
RIGHT
Fig.3 DAC and ADC data formats (continued in Fig.4).
1998 Jan 06
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
handbook, full pagewidth
LSB JUSTIFIED 48fs 16-BIT
BCK WS SDA LSB MSB LSB (a) I2S 48fs 16-BIT BCK WS SDA MSB LSB MSB (b) LSB MSB
MGE768
LEFT
RIGHT
MSB
LSB
LEFT
RIGHT
Fig.4 DAC and ADC data formats (continued from Fig.3).
There are different modes in which the UDA1309H can operate. These modes can be selected as shown in Table 3 and Fig.5. In mode a, the digital filters clock is switched off. Switching over to one of the ADC active modes (b, c or d) initiates a reset sequence of the digital filters. This mode should be activated immediately after power-on for at least 2 clock periods. Table 3 Operating mode selection DEVICE PIN LOGIC MODE a b c d e f g and h Note 1. X = don't care. not used record and playback record only record and analog loop-through analog loop-through playback only reserved DESCRIPTION ANLPTR 0 0 0 1 1 0 1 ADPON 0 1 1 1 0 0 X(1) DAPON 0 1 0 0 0 1 1
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
handbook, full pagewidth
MODE b
analog input
ADC ANALOG
ADC DIGITAL FILTER digital output
DAC DIGITAL FILTER digital input digital output
DAC ANALOG
analog output
MODE c
analog input
ADC ANALOG
ADC DIGITAL FILTER
MODE d
analog input
ADC ANALOG
ADC DIGITAL FILTER
digital output
analog output
MODE e
analog input
analog output
MODE f
digital input
DAC DIGITAL FILTER
DAC ANALOG
analog output
MGE771
Fig.5 Schematic diagram of operating modes.
1998 Jan 06
10
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA(AD) VDDA(DA) VDDO VDDD VDDD(F) VDD VSS VI IIK IOK Tstg Tamb Ves PARAMETER analog supply voltage (pin 8) analog supply voltage (pin 25) operational amplifiers supply voltage (pin 19) digital supply voltage (pin 28) digital filters supply voltage (pin 34) maximum supply voltage difference maximum ground supply voltage difference maximum input voltage DC clamp input diode current DC output clamp diode current; (output type 2 mA) storage temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k; 3 zaps positive and 3 zaps negative. 2. Machine model: C = 200 pF; L = 0.5 H; R = 10 ; 3 zaps positive and 3 zaps negative. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 60 VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V CONDITIONS - - - - - - - -0.5 - - -65 -20 -1500 -300 MIN.
UDA1309H
MAX. 6.5 6.5 6.5 6.5 6.5 100 100 V V V V V
UNIT
mV mV
VDD + 0.5 V 10 10 +150 +75 +1500 +300 mA mA C C V V
UNIT K/W
QUALITY SPECIFICATION In accordance with "SNW-FQ-611E". The number of this quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192.
1998 Jan 06
11
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
CHARACTERISTICS VDDD = VDDA = VDDO = VDDD(F) = 5 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 C; full scale sine wave input; mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless otherwise specified. SYMBOL Supply VDDA(AD) VDDA(DA) VDDO VDDD VDDD(F) IDDA(AD) IDDA(DA) IDDO ADC analog supply voltage (pin 8) DAC analog supply voltage (pin 25) operational amplifiers supply voltage (pin 19) ADC/DAC digital supply voltage (pin 28) digital filters supply voltage (pin 34) ADC analog supply current (pin 8) DAC analog supply current (pin 25) operational amplifiers supply current (pin 19) ADC power-down DAC power-down DAC power-down ADC power-down ADC/DAC power-down IDDD IDDD(F) ADC/DAC digital supply current (pin 28) digital filters supply current (pin 34) DAC power-down ADC power-down IDDD(F)q digital filters quiescent current 4.5 4.5 4.5 4.5 4.5 - - - - - - - - - - - - - 5.0 5.0 5.0 5.0 5.0 9 0.8 4.5 1.1 14 5.5 7.5 0 0.2 24 17 8 - 5.5 5.5 5.5 5.5 5.5 13.5 1.2 6.8 2.0 21 8.3 11.3 - 0.5 36 26 12 100 V V V V V mA mA mA mA mA mA mA mA mA mA mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1998 Jan 06
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-digital converter VI(rms) II VO RES input voltage (RMS value) input current (pins 13 and 14) unbalance between channels resolution 16-bit format 18-bit format (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB at -20 dB at -60 dB; A-weighted S/N cs PSRR idle channel signal-to-noise ratio channel separation power supply rejection ratio note 2 Vi = 0 V; A-weighted note 1 0.9 - - - - - - - tbf - - 1.0 - - 16 18 -85 -75 -35 95 90 -30 1.1 10 tbf - - tbf - -30 - - - V nA dB bits bits dB dB dB dB dB dB
Digital-to-analog converter VO(rms) VO RL CL RES output voltage (RMS value) unbalance between channels load resistance load capacitance resolution note 4 16-bit format 18-bit format (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB at -20 dB at -60 dB; A-weighted at -60 dB; A-weighted; note 5 S/N cs PSRR idle channel signal-to-noise ratio channel separation power supply rejection ratio note 2 code 0000H; A-weighted note 3 0.9 - 5 - - - - - - - - 90 - - - - - 1.0 0.1 - - 16 18 -90 -75 -38 -44 104 100 -30 -85 95 -1.1 1.0 1.1 - - 200 - - -82 - -34 - - - - - - - - V dB k pF bits bits dB dB dB dB dB dB dB
Analog loop-through (mode e) (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N Gltr Eos idle channel signal-to-noise ratio loop-through gain DC offset error at 0 dB VI = 0 V; A-weighted note 1 dB dB dB mV
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-digital decimation filter fs(o) fs(i) fsys B Asup output sample frequency input sample frequency system clock frequency signal bandwidth aliasing suppression fs(o) = 44.1 kHz fs(o) - B < fi < 2fs(o) - B; note 6 fi > 2fs(o) - B; note 6 OLdet fs(o) fs(i) fsys B SUP frequency response overload detection level fi = 20 Hz to 20 kHz note 7 28 - 256fs 0.02 60 80 -0.2 - - 28 256fs fs(i) = 44.1 kHz fi = 20 Hz to 20 kHz 0.02 -0.2 40 44.1 128fs - - - - - 0 54 - 256fs 20 - - +0.2 - - 54 256fs 20 +0.2 - kHz dB dB kHz kHz dB dB dB dB kHz
Digital-to-analog interpolation filter output sample frequency input sample frequency system clock frequency signal bandwidth frequency response out-of-band suppression 64fs 44.1 - - - 50
Digital part; note 8 INPUTS (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42 TO 44) VIL IIL IIH CI(max) LOW level input voltage LOW level input current HIGH level input current maximum input capacitance VI = VSSD VI = VDDD -0.5 - - - - - - - 0.3VDDD 10 10 10 V A A pF
INPUT (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42 TO 44) VIH VOL VOH IOZ HIGH level input voltage 0.7VDDD IOL = 2 mA IOH = -2 mA VO = VDDD or VSSD - VDDD - 0.5 - - - - - VDDD + 0.5 V 0.5 - 10 V V A
OUTPUTS (PINS 5 AND 41) LOW level output voltage HIGH level output voltage 3-state leakage current
1998 Jan 06
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
SYMBOL Timing
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BIT CLOCK (BCK) RELATED SIGNALS (see Fig.6); CLKEDGE = 0 Tcy tHC tLC tr tf tsuWS thWS tsuDA thDA thAD tdAD clock period clock HIGH time clock LOW time rise time fall time set-up time WS to rising edge of BCK hold time WS to rising edge of BCK set-up time SDA (DAC) to rising edge of BCK hold time SDA (DAC) to rising edge of BCK hold time SDA (ADC) to falling edge of BCK delay time SDA (ADC) to falling edge of BCK 300 100 100 - - 20 0 20 0 0 - - - - - - - - - - - - - - - 20 20 - - - - - 80 ns ns ns ns ns ns ns ns ns ns ns
SYSTEM CLOCK (SYSCLK) RELATED SIGNALS (see Fig.7) Tcy tHC tLC tr tf Notes 1. VI for full scale digital output is a function of VDDA(AD) [1.0 V (RMS) at VDDA(AD) = 5.0 V is equivalent to -1.0 dB in the digital domain]. 2. Vripple = 1% of the supply voltage and fripple = 100 Hz. 3. At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA). 4. For a load capacitance greater than 33 pF a series resistor of 200 is recommended. 5. 18 bits input data. 6. The aliasing suppression frequency is mirrored around 128fs. 7. VDDA = 5 V; indicated digital level is with respect to -1.0 dB (no overload). 8. All digital voltages = 4.5 to 5.5 V; all ground supply voltages = 0 V; Tamb = -20 to +75 C. clock period clock HIGH time clock LOW time rise time fall time 72 22 22 - - - - - - - - - - 10 10 ns ns ns ns ns
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
handbook, full pagewidth
Tcy tHC tLC VH BCK VL
CLKEDGE = 1
CLKEDGE = 0 tr tf tsuWS thWS
WS (LRCK)
tsuDA
thDA
SDA (DAC)
tdAD thAD
SDA (ADC)
MGE769
Fig.6 Serial timing of BCK related signals.
1998 Jan 06
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
handbook, full pagewidth
Tcy tHC tLC
SYSCLK
tr
tf
MGE770
Fig.7 Serial timing of SYSCLK related signals.
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
UDA1309H
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Jan 06
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
UDA1309H
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
UDA1309H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
NOTES
UDA1309H
1998 Jan 06
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
NOTES
UDA1309H
1998 Jan 06
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Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
NOTES
UDA1309H
1998 Jan 06
23
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
Internet: http://www.semiconductors.philips.com
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/02/pp24
Date of release: 1998 Jan 06
Document order number:
9397 750 03167

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